Instruction systolic array (ISA)

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The instruction systolic array (ISA) is an architectural concept for array computers suited to very high integration technology. Some basic publications concerning the ISA architecture and applications are listed in the following.

[KLSSS 88]M. Kunde, H.W. Lang, M. Schimmler, H. Schmeck, H. Schröder: The Instruction Systolic Array and its Relation to Other Models of Parallel Computers. Parallel Computing 7, 25-39 (1988)
[Lan 86]H.W. Lang: The Instruction Systolic Array, a Parallel Architecture for VLSI. Integration, the VLSI Journal 4, 65-74 (1986)
[Lan 87]H.W. Lang: ISA and SISA: Two Variants of a General Purpose Systolic Array Architecture. In: L.P. and S.I. Kartashev (eds.): Proc. Second Int. Conf. on Supercomputing, Vol. 1, 460-465 (1987)
[Lan 88]H.W. Lang: Transitive Closure on the Instruction Systolic Array. In: K. Bromley, S.Y. Kung, E. Swartzlander (eds.): Proceedings of the Int. Conf. on Systolic Arrays, San Diego, Computer Society Press, Washington D.C., 295-304 (1988)
[SchSch 91]M. Schimmler, H. Schmeck: A Fault-Tolerant and High Speed Instruction Systolic Array. Proc. International. Conference on VLSI '91, Edinburgh, Scotland (1991)
[Schi 87]M. Schimmler: Fast Sorting on the Instruction Systolic Array. Bericht Nr. 8709, Institut für Informatik, Christian-Albrechts-Universität Kiel (1987)
[Schi 92]M. Schimmler: Instruction Systolic Arrays -- Experiences With a First Implementation. ISCA '92, Hamilton Island, Australia (1992)
[Schi 94]M. Schimmler: The Instruction Systolic Array -- Implementation of a Low-Cost Parallel Architecture as Add-On Board for Personal Computers. Proceedings High Performance Computing and Networking, München (1994)
[SchL 96]M. Schimmler, H.W. Lang: The Instruction Systolic Array in Image Processing Applications. In: O. Loffeld (ed.): Vision Systems: Sensors, Sensor Systems and Components, Proc. SPIE Vol. 2784, 136-144 (1996)
[HHL 96]R.S. Hogg, W.I. Hughes, D.W. Lloyd: A Novel Asynchronous ALU for Massively Parallel Architectures. 4th Euromicro Workshop on Parallel and Distributed Processing, 282-292 (1996)
[SSS 97]B. Schmidt, M. Schimmler, H. Schröder: Morphological Hough Transform on the Instruction Systolic Array. In: C. Lengauer, M. Griebl, S. Gorlatch, (eds.), EuroPar '97, Lecture Notes in Computer Science 1300, Springer, 798-806 (1997)
[SSS 98a]B. Schmidt, M. Schimmler, H. Schröder: The Instruction Systolic Array in Tomographic Image Reconstruction Applications. Proceedings PART '98, Adelaide, Australia, Springer (1998)
[SSS 98b]B. Schmidt, M. Schimmler, H. Schröder: Long Operand Arithmetic on Instruction Systolic Computer Architectures and its Applications in Cryptography. EuroPar '98, Lecture Notes in Computer Science 1470, Springer, 916-922 (1998)
[SSS 01]B. Schmidt, H. Schröder, M. Schimmler: Protein Sequence Comparison on the Instruction Systolic Array. Parallel Computing Technologies '01, Lecture Notes in Computer Science 2127, Springer, 498-509 (2001)
[SSL 04]M. Schimmler, B. Schmidt, H.W. Lang : A Bit-Serial Floating Point Unit for a Massively Parallel System on a Chip. Parallel Algorithms and Applications, 19, 2-3, 79-96 (2004)

 

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