Instruction systolic array (ISA)

Processor architecture and instruction set


Bit-serial processor architecture

The main components of the processor architecture are a set of 56 data registers, the communication register, a unit for integer addition and logic operations, a unit for conditional instructions, a 16-bit multiplier, and a shifter/adder for floating point operations. Figure 1 shows a block diagram of the architecture.

Block diagram of the processor architecture
Figure 1:  Block diagram of the processor architecture

The data word length is 16 bits. Data are processed bit-serially, such that the execution of each instruction takes exactly 16 clock cycles. However, there are macro instructions formed as series of elementary instructions in order to handle data types consisting of more than one machine word, e.g. double precision floating point numbers.

After receiving an instruction, the processor stores it in the instruction register, decodes the addresses of the two operands op0 and op1 and of the destination dest, retrieves the operands from the register file, executes the instruction opc, writes the result back to the destination register, and passes the instruction to the next processor. A so-called r-bit accompanies bit 0 of each instruction and controls these phases of instruction execution.

Since all this is done bit-serially, it can be pipelined on bit level, such that a new instruction is fetched and processed every 16 clock cycles. For instance, the first bit of the result is computed immediately after the second bits of the operands have entered the respective unit. As the register file is implemented as a RAM, a byte-parallel access is in this case more appropriate than bit-serial operation (Figure 2).

Bit-level pipelined execution of an instruction
Figure 2:  Bit-level pipelined execution of an instruction


Instruction set

The instructions are 3-address instructions coded in two 16-bit words. The two operand registers op0 and op1 may be one of the 56 registers, the communication register, the communication register of one of the four direct neighbours, the constants 0 or -1, or the special register LDC. The destination register dest may be one of the 56 registers, the communication register, an index register, the constant 0, or one of the special registers AF, RD, and SCR. It is also possible to write into one of the 56 registers and the communication register simultaneously.

The simplest instruction is an addition of two 16-bit integer operands

add    op0, op1, dest

This operation takes the contents of registers op0 and op1, performs an addition, and stores the result in register dest. As the result is computed, it is checked for being zero or negative, in which cases the zero flag Z or the negative flag N are set. Similar instructions exist for the subtraction (sub) and the logical functions (and, or, nand, nor, xor, eqv).

The zero flag Z can be tested with the instruction

ifz    op0, op1, dest

which performs a conditional assignment of the form dest:=if Z then op0 else op1. A similar instruction exists for testing the negative flag N. Conditional instructions do not change the flags themselves.

An unconditional assignment of the form dest:=op0 can be achieved in two ways: by the assignment instruction

set    op0, dest

or with the logical instruction

or     op0, 0, dest

In the latter case the flags are changed, while in the first case they are not. A no-operation instruction is realized by addressing the constant 0 as the destination register:

set    0, 0

For integer operands longer than 16 bits there are special addition/subtraction instructions adc and sbc that take into account the carry bit of a preceding addition or subtraction. E.g. by the sequence of instructions

add    R0, R2, R4
adc    R1, R3, R5

two 32-bit operands are added (the contents of R0,R1 and R2,R3, respectively). The result is written to R4,R5.

The most frequent constants 0 and -1 can be addressed directly. Other constants can be loaded into a register by the load immediate instruction

ldi    constant, dest

By writing a 0 into the special register AF, a processor can make itself inactive (sleep). The effect is that this processor does not execute any instruction, except of the special instruction


which makes it active again. This concept is a data dependent supplement to the row and column selector masking mechanism.

Several instructions are related to floating point operations. However, these instructions in general do not make sense on their own, but only within a macro instruction, i.e. a sequence of instructions that realize a certain operation on floating point numbers. The instruction

expadd  op0, op1, dest

computes the sum of the exponents of two floating point numbers, as required for a multiplication. Similarly, there exist instructions expsub for computing the difference of two exponents and expsel for selecting the greater exponent as the result exponent in the case of an addition of two floating point numbers.

The instructions shadd (shift and add), shsub (shift and subtract), nrm (normalize), ldmul (load multiplier), and mul (multiply) are used in macro instructions for computing the mantissa of the result. The instruction

mode   length

is used for configuration of the floating point unit for handling single precision or double precision numbers. The instructions

mtw    op0, dest
expw   op0, dest

support the conversion between the IEEE floating point format and the internal format.

Finally, the instruction

bank   i

is used to switch the banks of I/O registers. If i element {0, 1}, bank i can be accessed from the processor array and bank 1-i from outside via a global bus. If i = 2, the banks are toggled.



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